作者: John R. Kloeppner , Daniel P. Leak
DOI:
关键词: Process (computing) 、 Error detection and correction 、 Code (cryptography) 、 Word (computer architecture) 、 Computer science 、 Computer hardware 、 Multistage amplifier 、 Generator (computer programming) 、 Transfer (computing) 、 Cyclic redundancy check
摘要: An error correction code (ECC) generator/checker for processing high bandwidth data block transfers. The ECC logic includes a plurality stages, each stage including Reed-Solomon Cyclic Redundancy Check (RS CRC) single word. stages can be configured to operate in parallel process multiple-word parallel, transfers, or individually wherein processes word-serial manner. Each first input receiving respective word portion of transfer, second either an intermediate value from previous feed back value, means combining words received at the and inputs, alpha multiplier output providing When mode are connected series such that is stage, third so on. final fed stage. manner, its input.