High speed parallel CRC device for concatenated data frames

摘要: A cyclic redundancy check generator for a high speed data bus is capable of outputting frames and bits concatenated together without any additional space or time delay between while operating at normal clock speed. Data to be transmitted parallel loaded into series-connected registers via multiplexers connected the registers. The also provide loading frame from look-ahead logic circuit. output circuit register. has inputs final register operates on portions words in when last portion word been processed, selected by then shifted out immediately behind frame. After have register, first next initialized so that processing can begin