Hiding Relaxed Memory Consistency with Compilers

摘要: We present a compiler technique, which is based on Shasha and Snir's delay set analysis, to hide the underlying relaxed memory consistency model for an optimizing explicitly parallel programs. The presents programmers with sequentially consistent view of machine irrespective whether it follows or model. To guarantee sequential consistency, our algorithm inserts fence instructions by identifying memory-barrier nodes. r educe number exploiting ordering constraints property synchronization operations. introduce dominators respect node in control flow graph identify also show that minimizing nodes using NP-hard.