Automated Mapping of Coarse-Grain Pipelined Applications to FPGA Systems

摘要: Configurable systems offer a unique opportunity to define application-specific architectures. These architectures performance advantages, where the use of customized pipelines exploits inherent parallelism application. In this research, we describe set program analyses and an implementation that automatically map sequential un-annotated C into pipelined targeted FPGA with multiple external memories. This research describes automated approach hardware design space exploration, through collaboration between parallelizing compiler technology high-level synthesis tools. previous work, described algorithm optimizes individual loop nests, expressed in C, derive efficient implementation. global optimization strategy maps nests coarse-grain