Which interconnects for which 3D applications? Status and perspectives
作者： Y. Lamy , J.P. Colonna , G. Simon , P. Leduc , S. Cheramy
DOI: 10.1109/3DIC.2013.6702344
关键词: Electronics 、 Integrated circuit packaging 、 Materials science 、 Electrical engineering 、 Low volume 、 Interposer 、 Fine pitch 、 Integrated circuit design
摘要: Some 3D interconnects technologies are reviewed and discussed in this paper with respect to emerging applications. While 2.5D Si interposer packaging seem rely cu pillars for the coming years, very fine pitch below 10μm will be mandatory 3DIC many options like cu-cu bonding or μ-tubes race. Specific RF/mm-waves low volume electronics devices also relevant examples.
sci-hub.se 参考文章(18)
L. Sanchez, L. Bally, B. Montmayeul, F. Fournel, J. Dafonseca, E. Augendre, L. Di Cioccio, V. Carron, T. Signamarcheix, R. Taibi, S. Mermoz, G. Lecarpentier, Chip to wafer direct bonding technologies for high density 3D integration 2012 IEEE 62nd Electronic Components and Technology Conference. pp. 1960- 1964 ,(2012) , 10.1109/ECTC.2012.6249108
D. Henry, J. Charbonnier, P. Chausse, F. Jacquet, B. Aventurier, C. Brunet-Manquat, V. Lapras, R. Anciant, N. Sillon, B. Dunne, N. Hotellier, J. Michailos, Through Silicon Vias Technology for CMOS Image Sensors Packaging: Presentation of Technology and Electrical Results electronics packaging technology conference. pp. 35- 44 ,(2008) , 10.1109/EPTC.2008.4763409
Rebha El Farhane, Myriam Assous, Patrick Leduc, Aurelie Thuaire, David Bouchu, Helene Feldis, Nicolas Sillon, A successful implementation of dual damascene architecture to copper TSV for 3D high density applications ieee international d systems integration conference. pp. 1- 4 ,(2010) , 10.1109/3DIC.2010.5751445
Jean-Philippe Colonna, Perceval Coudrain, Gennie Garnier, Pascal Chausse, Roselyne Segaud, Christophe Aumont, Amandine Jouve, Nicolas Hotellier, Thomas Frank, Catherine Brunet-Manquat, Severine Cheramy, Nicolas Sillon, Electrical and morphological assessment of via middle and backside process technology for 3D integration electronic components and technology conference. pp. 796- 802 ,(2012) , 10.1109/ECTC.2012.6248924
A. Garnier, C. Gremion, R. Franiatte, D. Bouchu, R. Anciant, S. Cheramy, Investigation of copper-tin transient liquid phase bonding reliability for 3D integration electronic components and technology conference. pp. 2151- 2156 ,(2013) , 10.1109/ECTC.2013.6575878
Jean-Charles Souriau, Laetitia Castagne, Jean-Luc Liotard, Karim Inal, Jessica Mazuir, Francois Le Texier, Gilles Fresquet, Maxime Varvara, Nicolas Launay, Beatrice Dubois, Thierry Malia, 3D multi-stacking of thin dies based on TSV and micro-inserts interconnections electronic components and technology conference. pp. 1047- 1053 ,(2012) , 10.1109/ECTC.2012.6248965
J P Colonna, R Segaud, F Marion, M Volpert, A Garnier, L Di Cioccio, Y Beillard, S Mermoz, F De Crecy, C Laviron, S. Cheramy, Towards alternative technologies for fine pitch interconnects electronic components and technology conference. pp. 872- 878 ,(2013) , 10.1109/ECTC.2013.6575676
S. Joblot, P. Bar, H. Sibuet, C. Ferrandon, B. Reig, S. Jan, C. Arnaud, Y. Lamy, P. Coudrain, R. Coffy, O. Boillon, J.F. Carpentier, Copper pillar interconnect capability for mmwave applications in 3D integration technology Microelectronic Engineering. ,vol. 107, pp. 72- 79 ,(2013) , 10.1016/J.MEE.2012.10.024
H. Moriceau, F. Rieutord, F. Fournel, L. Di Cioccio, C. Moulet, L. Libralesso, P. Gueguen, R. Taibi, C. Deguet, Low temperature direct bonding: An attractive technique for heterostructures build-up Microelectronics Reliability. ,vol. 52, pp. 331- 341 ,(2012) , 10.1016/J.MICROREL.2011.08.004
Robert Wieland, Detlef Bonfert, Armin Klumpp, Reinhard Merkel, Lars Nebrich, Josef Weber, Peter Ramm, 3D Integration of CMOS transistors with ICV-SLID technology Microelectronic Engineering. ,vol. 82, pp. 529- 533 ,(2005) , 10.1016/J.MEE.2005.07.052