作者: Dean Tullsen , Rakesh Kumar
DOI:
关键词: Degradation (telecommunications) 、 Multi-core processor 、 Interconnection 、 Engineering 、 Distributed computing 、 Inefficiency 、 Core (game theory) 、 Parallel computing 、 Architecture 、 Marginal utility 、 Replication (computing)
摘要: Increasing design complexity and diminishing marginal utility of monolithic processor designs has resulted in integration multiple loosely-coupled processing cores on the same die. However, fundamental questions remain about right form, implementation, methodology for multi-core designs. This thesis addresses these questions. A popular designing a architecture is to replicate an off-the-shelf core times, then connect together using interconnect mechanism. this "multi-core oblivious" as subsystems are designed/optimized unaware overall chip-multiprocessing system they would become parts of. demonstrates that very inefficient terms area/power, recommends holistic approach where designed from ground up different components full system. Inefficiency comes at levels. Having replicated results inability adapt demands execution workloads, either underutilization or overutilization resources. proposes single-ISA (instruction-set architecture) heterogeneous architectures die hosts varying power/performance characteristics, but all capable running ISA. Such can result significant power savings performance improvements if applications mapped judiciously. The also presents methodologies such architectures. Another source inefficiency blind replication over-provisioned hardware structures. To effect, conjoined-core chip multiprocessing adjacent share some shows area without much degradation. novel optimizations minimizing already small Yet another interconnection. interconnection overheads be design---especially number increases pipelines get deeper. need co-design cores, memory obviate problem, makes several suggestions regarding co-design.