Vertical device 4F2 EEPROM memory

摘要: EEPROM memory devices and arrays are described that facilitate the use of vertical floating gate cells select gates in NOR or NAND high density architectures. Memory embodiments present invention utilize to form architecture cell strings, segments, arrays. These architectures allow for improved with integral can take advantage feature sizes semiconductor fabrication processes generally capable appropriate device sizing operational considerations. The also mitigation disturb overerasure issues by placing behind isolate from their associated bit lines and/or source lines.