Programmable memory decode circuits with transistors with vertical gates

摘要: Structures and methods for programmable memory decode circuits are provided with logic cells, or floating gate transistors, which can operate lower applied control voltages than conventional circuits. The arrays of the present invention do not increase costs complexity fabrication process. According to teachings invention, capacitance in cells is much smaller such that majority any voltage will appear across thin tunnel oxide. include a number address lines output lines, form an array. A disposed at intersections lines. non volatile least one redundant line. source region, drain channel region separating regions horizontal substrate. first vertical located above portion separated from by thickness insulator material. second another therefrom