Reducing the pin count within a switching element through the use of a multiplexer

摘要: The present invention comprises a system and method for reducing the pin count between plurality of MAC PHY devices within switching element. In this embodiment, element includes general serial interfaces providing connections respective each operates at first data rate. multiplexer coupled to pad member including pins. is receives multiplexed signals from interfaces. second rate that multiple Generally, in accordance with allows multiplexing purpose interface (GPSI) reduce some cases by as much 75% also synchronize MAC/PHY interface. example, uses total 7 pins supports four connections. If only GPSIs were utilized, 28 would be required function. same technique will 100 Mbps 56 port 18 example operate times speed