System and method for automated simulator assertion synthesis and digital equivalence checking

摘要: A system, method, and computer program product for automatically generating equivalent assertions in different forms verification tools, which may be analog or digital. user submits a set of logic that, if unclocked, are converted to clocked by skewing clocks ensure simulator uniformity. stimulus is generated, perhaps at random, input. test bench either input synthesized. For each tool, the simulated simulation results captured. An assertion status difference engine evaluates result differences between identifies outputs indicating significant inconsistency. Errors tool implementation coding can detected. The simulators used include SPICE Verilog, any other that differ type, algorithm, format, vendor implementation.