System and method for extracting parasitic impedance from an integrated circuit layout
作者： Keh-Jeng Chang , Martin Walker , Douglas Kaufman
DOI:
关键词: Signal 、 Engineering 、 Electronic circuit simulation 、 RC circuit 、 Interconnection 、 Solver 、 Integrated circuit 、 Electrical impedance 、 Electronic engineering 、 Integrated circuit layout
摘要: A comprehensive system and method allow an integrated circuit designer to extract accurate estimates of parasitic impedances in interconnection lines circuit. The includes collecting values electrical characteristic parameters provide a technology profile for particular fabrication process. An Interconnect Primitive Library builder provides collection interconnect `primitives` that any structure fabricated under the process can be broken down into, combines it with simulations 3-dimensional field solver parameterized coupling capacitances other each primitive. extraction tool traces signal path decomposes structures on into primitives maps them Library. RC network module based characterized parametric mapped primitives. thus provided used accurately estimate delays simulator or delay calculator.
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