Method for fabricating a sub-half micron MOSFET device with insulator filled shallow trenches planarized via use of negative photoresist and de-focus exposure
作者： Hong-Chang Dai , Chang-Ming Dai , Shih-Chang Tai
DOI:
关键词: MOSFET 、 Insulator (electricity) 、 Nanotechnology 、 Trench 、 Chemical-mechanical planarization 、 Materials science 、 Photoresist 、 Optoelectronics
摘要: A process for globally planarizing the insulator used to fill narrow and wide shallow trenches, in a MOSFET device, structure, has been developed. The features smoothing topography that exists after filling of by creating photoresist plugs, only depressed regions. This is accomplished using negative layer, de-focus exposure, identical mask create trench pattern positive layer. RIE procedure, with 1:1 etch selectivity, complete planarization process.
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