Multiple-gate transistors with improved gate control
作者： Fu-Liang Yang , Chenming Hu , Yee-Chia Yeo
DOI:
关键词: Insulator (electricity) 、 Electronic engineering 、 Gate oxide 、 Gate dielectric 、 Transistor 、 Semiconductor 、 Materials science 、 Gate control 、 Electrically conductive 、 Undercut 、 Optoelectronics
摘要: A method for fabricating a multiple-gate device including the steps of providing substrate semi-conducting layer on an insulator stack which includes overlying etch-stop layer; patterning forming semiconductor fin; etching at base fin undercut; depositing gate dielectric electrically conductive over straddling across two sidewall surfaces and top surface source region drain in fin.
lens.org 参考文章(5)
Mark Visokay, Antonio Rotondaro, Luigi Colombo, Malcolm Bevan, CVD deposition of M-SION gate dielectrics ,(2002)
Bruce B. Doris, Sadanand V. Deshpande, William H. Ma, Rajarao Jammy, Method of fabricating SiO2 spacers and annealing caps ,(2001)
Jyh-Chyurn Guo, Gate stack for high performance sub-micron CMOS devices ,(2001)
Ghavam Shahidi, Tze-Chiang Chen, Fariborz Assaderaghi, Edward Nowak, K. Muller, Soi transistor with polysilicon seed ,(2001)
Srikanth B. Samavedam, William J. Taylor, Christopher C. Hobbs, Transistor having a high K dielectric and short gate length and method therefor ,(2001)