Dual pipe cache memory with out-of-order issue capability

摘要: A data cache memory apparatus permits load and store instructions to be issued out-of-order. The includes a memory. An instruction issue issues an stream containing instructions. are completed in two passes, namely allocate pass corresponding commit pass. control is connected the addresses response from apparatus. history table stores record of where stored, thus passes by for which no has been completed. responds subsequent address clear table. If designates but not yet issued, determines conflict reissued. Provision made retrieving secondary clearing upon detection branch error.