Method and system for detecting bypass errors in a load/store unit of a superscalar processor

摘要: A load queue is provided in a load/store unit of superscalar processor that includes real page number buffer for storing each instruction entry the queue. The also comparator coupled to comparing executing entries with queued further cache line modified register data cache. marks when addressed by has been modified. In preferred embodiment, out program order respect one instructions, and marked instruction, signals sequencer cancel instruction. an identification identifier buffer. compares ordering or store