Ensuring data integrity by locked-load and conditional-store operations in a multiprocessor system

摘要: A high performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed size, and permits only simplified memory access data width addressing modes. The set is limited to register-to-register operations register load/store operations. Byte manipulation instructions, included permit use previously-established structures, include facility for doing in-register byte extract, insert masking, along with non-aligned load store instructions. provision load/locked store/conditional instructions implementation atomic writes.