Cache system using mask bits to recorder the sequences for transfers of data through cache to system memory

作者: David W. Siegel , Sudhir Dhawan , Ravi K. Arimilli

DOI:

关键词: Parallel computingCache coloringCache invalidationCache-oblivious algorithmSmart CacheCacheCache pollutionPage cacheCache algorithmsComputer hardwareComputer science

摘要: Apparatus and method for improving the rate of transfer data in context a system memory operated conjunction with cache. In one form, mask bits bit register are associated to bytes The changed state when corresponding byte cache is written. used reordered operating sequence selectively write from into after Data performance improved significantly that selective writing can be completely eliminated indicate whole unit cache, typically line, has been written during

参考文章(18)
Tetsu Igarashi, Cache memory control apparatus ,(1986)
Norman H Kreitzer, Francis Paul Carrubba, George Radin, John Cocke, A hierarchical memory system including separate cache memories for storing data and instructions ,(1983)
Yasuhiko Saigou, Kunio Uchiyama, Takashi Kikuchi, Kanji Oishi, Hirokazu Aoki, Hiroshi Fukuta, Tadahiko Nishimukai, Katsuyuki Sato, Susumu Hatano, Single chip cache with partial-write circuit for transferring a preselected portion of data between memory and buffer register ,(1989)
Yasuhiko Saigou, Kunio Uchiyama, Takashi Kikuchi, Kanji Oishi, Hirokazu Aoki, Hiroshi Fukuta, Tadahiko Nishimukai, Katsuyuki Sato, Susumu Hatano, Single-chip-cache-buffer for selectively writing write-back and exclusively writing data-block portions to main-memory based upon indication of bits and bit-strings respectively ,(1992)
Tsutomu Sumimoto, Toshihisa Taniguchi, Takashi Kumagai, Memory access control system and method for an information processing apparatus ,(1985)