Low power consumption integrated circuit for a combined timepiece and calculator
作者： Toshio Nishimura , Shintaro Hashimoto
DOI:
关键词: Clock skew 、 Clock domain crossing 、 Clock signal 、 Clock rate 、 Computer hardware 、 Electronic engineering 、 Digital clock manager 、 Computer science 、 Synchronous circuit 、 CPU multiplier 、 Clock gating
摘要: An integrated circuit device having a combined time-keeping mode and calculator comprises generator stage for generating basic clock signals system signals, processor responsive to supply of the executing arithmetic operations required timekeeping key input members introducing information into as control controlling signals. The is adapted develop command signal indicate completion operations. rising trailing edges enabling generation causes prevent from being fed stage.
lens.org 参考文章(2)
Nunzio A. Luce, Electronic calculator watch structures ,(1974)
Ronald W. Streiber, Donald L. McLaughlin, Reducing power consumption in calculators ,(1974)