作者: Ching I Chen , Yu Zhen Liu , Jian Wei Chen
DOI: 10.4028/WWW.SCIENTIFIC.NET/AMM.229-231.434
关键词: Structural engineering 、 Interposer 、 Stack (abstract data type) 、 Substrate (building) 、 Taguchi methods 、 Integrated circuit 、 Die (integrated circuit) 、 Temperature cycling 、 Composite material 、 Soldering 、 Engineering
摘要: To achieve high density and performance, through-Silicon Vias (TSVs) have recently aroused much interest because it is a key enabling technology for three-dimensional (3-D) integrated circuit stacking silicon interposer technology. In this study, 3-D 1/8th symmetrical nonlinear finite element model of stack die TSV package was developed using ANSYS simulation. The used to optimize the robust design determine rules enhance in view bump reliability. An L8(2×7) Taguchi matrix investigate effects thickness, diameter, insulation (SiO2) chip substrate height, diameter on bumps A temperature cycling test range 0 °C 100 conducted by three cycles. mechanical property SAC leadless solder included time independent plastic dependent creep behaviors. parameter inelastic strain third cycle evaluate life prediction. Two levels were chosen each cover ranges interest. results show that smaller thickness larger dimension other factors provide best combination. These could be as guides further similar packages design.