Exploiting Word-Width Information During Mapping

摘要: Optimizing the energy efficiency of an embedded platform has to be tackled at different abstraction levels and for all relevant components. In previous chapters we have seen that components initially dominate power/energy pie chart been one by reduced with a substantial factor: instruction memory organisation, data background hierarchy foreground memory. As result, bottleneck in power should now also strongly influenced toward last component (single-core) platform. Hence, this chapter move our focus processor datapath. The main objective is use word-width information order reduce consumption datapath operations processor-based systems (both traditional instruction-set coarse grained reconfigurable processors).