Power efficient dynamic-range utilisation for DSP on FPGA

摘要: A power and resource efficient dasiadynamic-range utilisationpsila technique to increase operational capacity of DSP IP cores by exploiting redundancy in the data representation sampled analogue input data, is presented. By cleverly partitioning dynamic-range into separable processing threads, several streams are computed concurrently on same hardware. Unlike existing techniques which act solely reduce consumption due sign extension, here dynamic range exploited while still achieving reduced consumption. This extends an system-level, framework for design low cores, when applied FFT core a digital receiver system gives architecture requiring 50% fewer multipliers, 12% slices 51%-56% less power.