Interprocessor communications data transfer and error detection in a multiprocessing environment

摘要: A multiprocessing system includes a plurality of data processing subsystems each coupled to an interprocessor communications bus through corresponding interface. The interface subsystem receive FIFO buffer unit, transmit and control circuit. When desires transfer another subsystem, the packetizes in variable word-length packet which header having size field target field. causes be stored within unit. valid is with particular associated unit requests mastership packet. interfaces remaining decode information conveyed first byte cycle. If during given cycle corresponds assigned value programmed for interface, that operates receiver.