Digital-circuit analysis of short-gate tunnel FETs for low-voltage applications

摘要: This paper investigates the potential of tunnel field-effect transistors (TFETs), with emphasis on short-gate TFETs, by simulation for low-power digital applications having a supply voltage lower than 0.5 V. A transient study shows that tunneling current has negligible contribution in charging and discharging gate capacitance TFETs. In spite higher resistance region TFET, (dis)charging speed still meets low-voltage application requirements. circuit analysis is performed TFETs different materials, such as Si, Ge heterostructures terms overshoot, delay, static power, energy consumption delay product (EDP). These results are compared to MOSFET full-gate TFET performance. It concluded heterostructure (Ge–source nTFET, In0.6Ga0.4As–source pTFET) promising candidates extend V because they combine advantage low Miller capacitance, due structures, strong drive narrow bandgap material source. At 0.4 an EOT channel length 0.6 nm 40 nm, respectively, three-stage inverter chain based saves 40% per cycle at same 60%–75% improvement EDP its counterpart. When MOSFET, better can be achieved especially power consumption.