作者: Simone Ferri
DOI:
关键词: Upstream (networking) 、 Signal 、 Pulse-width modulation 、 Delta-sigma modulation 、 Dither 、 Block (data storage) 、 Function (mathematics) 、 Control theory 、 Signal transfer function 、 Engineering
摘要: The circuit includes, upstream from a PWM quantizer, that is between the output of sigma-delta modulator and input or PWM-like second ancillary stage any order architecture, with function controlling minimum dynamic modulator. This signal summed to corresponding difference stage, delayed by delay block.