作者: J.-P. Manceau , S. Bruyere , E. Picollet , M. Minondo , C. Grundrich
DOI: 10.1109/ICMTS.2006.1614303
关键词: Chip 、 Voltage 、 Relaxation (physics) 、 Molecular physics 、 Dielectric 、 Frequency domain 、 Permittivity 、 Electronic engineering 、 Capacitor 、 Materials science 、 Capacitance
摘要: This paper deals with 5fF//spl mu/m/sup 2/ Ta/sub 2/O/sub 5/ MIM (metal-insulator-metal) dielectric relaxation characterization and modeling. The Dow model based on RC poles is reviewed in particular to introduce temperature behavior. An optimized test chip that can be accurately simulated allows us properly measure memory effect. enables obtained over 5 time decades the whole voltage operation range. good agreement of this capacitance versus frequency measurements validates approach.