Method and apparatus for sampling and holding an analog input voltage which eliminates offset voltage error

摘要: A sample and hold circuit uses two amplifiers the second being a Miller integrator first comparator which compares feed back stored capacitor voltage to sampled bring of value. This will have included in it offset amplifier. However on readout this is eliminated by disconnecting input also connection between output amplifier instead connecting taking from interconnection line. Since noninverting or plus terminal has impressed upon unwanted effectively subtracted. The foregoing finds preferred use 12 bit recirculating D converter where cumulative errors would cause error. In such configuration one circuits can feedback configured perform suitable multiplication subtraction, for example, Gray code. Here stores successive computational results.