Gated integrator with signal baseline subtraction

摘要: An ultrafast, high precision gated integrator includes an opamp having differential inputs. A signal to be integrated is applied one of the inputs through a first input network, and indicative DC offset component other second network. pair electronic switches in networks define integrating period when they are closed. The substantially symmetrically constructed matched components so that error introduced by appear both circuits and, hence, nullified common mode rejection opamp. provided sample hold circuit actuated as begins. symmetrical configuration improves accuracy speed balancing out errors, permitting use switching elements opamps small time constant. eliminates caused baseline during single window.