Memory controller and memory access system with error detection using data comparison of loop-backed signals
作者： Miho Takeda , Hisataka Nakabayashi , Masanori Ito
DOI:
关键词: Signal 、 Loop (topology) 、 Section (archaeology) 、 Comparator 、 Error detection and correction 、 Signal transfer function 、 Controller (computing) 、 Electronic engineering 、 Memory controller 、 Algorithm 、 Computer science
摘要: A controller section outputs a first signal and second holding phase relationship with the signal. The is received by memory I/F via FIFO of an error detecting section. performs timing adjustment for signals, signals after to memory, loops back data comparator compares looped-back original outputted from corresponding
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