Alignment of recovered clock with data signal
作者： Shoujun Wang , Tad Kwasniewski , Haitao Mei , Bill Bereza , Mashkoor Baig
DOI:
关键词:
摘要: A recovered clock signal is aligned (“eye centered”) with a data from which it by intentionally varying one of the factors or parameters that causes misalignment. For example, if loop circuit (i.e., phase-locked delay-locked loop) used to recover signal, charge pump current mismatch in normally factor clock-data misalignment, and also parameter can be manipulated. During test mode, varied obtain best error rate, signifies alignment. The mode implemented using built-in self-test circuitry already on device transmit then receive analyze for errors.
lens.org 参考文章(24)
Sven Erik Wahlstrom, Electronically controlled microelectronic cellular logic array ,(1966)
Wesley Calvin d'Haene, Atul Krishna Gupta, Non-linear phase detector ,(2001)
Ramanand Venkata, Chong H. Lee, Digital phase locked loop circuitry and methods ,(2004)
Ramanand Venkata, Chong H. Lee, Byte alignment circuitry ,(2002)
Richard G. Cliff, Cameron McClintock, James Schleicher, Manuel Mejia, Bruce B. Pedersen, Srinivas T. Reddy, Andy L. Lee, David E. Jefferson, Christopher F. Lane, Programmable logic device architectures with super-regions having logic regions and a memory region ,(2002)
Ramanand Venkata, Rakesh Patel, Chong H Lee, Programmable logic devices with multi-standard byte synchronization and channel alignment for communication ,(2005)
Peter A. Franaszek, Albert X. Widmer, Byte oriented dc balanced (0,4) 8b/10b partitioned block transmission code ,(1982)
Shahriar Rokhsaz, Ahmed Younis, Brian T. Brunn, Clock and data recovery phase-locked loop ,(2003)
Richard G. Cliff, Bonnie I. Wang, Chiakang Sung, Joseph Huang, Phase-locked loop circuitry for programmable logic devices ,(1999)
Chong H. Lee, Reza Asayesh, Programmable logic device with high speed serial interface circuitry ,(2002)