作者: Yasuhiro Ogasahara , Toshihiro Sekigawa , Masakazu Hioki , Tadashi Nakagawa , Toshiyuki Tsutsumi
DOI: 10.1109/ICMTS.2015.7106154
关键词: Structure based 、 Reduction (complexity) 、 Engineering 、 Process (computing) 、 Voltage 、 Overhead (computing) 、 Device simulation 、 Electronic engineering
摘要: This paper presents the significant reduction of area overhead due to triple-well structure for adaptive body bias methods. Triple-well TEGs which include violation design rules originating from voltage tolerance were implemented on a 65nm process. Reexamining based measurement results reduced deep n-wells spacing by 60% A new method further is proposed device simulation validated with results.