Asynchronous 3D-NoCs Making Use of Serialized Vertical Links

作者: Abbas Sheibanyrad , Frédéric Pétrot , Axel Jantsch

DOI: 10.1007/978-1-4419-7618-5_7

关键词: Key (cryptography)Computer scienceAsynchronous communicationAsynchronous circuitNetwork performanceDie (integrated circuit)Distributed computingDomain (software engineering)Integrated circuitElectronic circuitTechnology & EngineeringSoftware Development & EngineeringElectronicsCircuitsElectricalGeneralComputers

摘要: This book presents the research challenges that are due to the introduction of the 3rd dimension in chips for researchers and covers the whole architectural design approach for 3D-SoCs. Nowadays the 3D-Integration technologies, 3D-Design techniques, and 3D-Architectures are emerging as interesting, truly hot, broad topics. The present book gathers the recent advances in the whole domain by renowned experts in the field to build a comprehensive and consistent book around the hot topics of three-dimensional architectures and micro-architectures. This book includes contributions from high level international teams working in this field.

参考文章(21)
Giovanni De Micheli, Networks on chip IEEE Computer. pp. 105- 110 ,(2003) , 10.1007/978-1-4020-6488-3_8
Pierre Guerrier, Alain Greiner, A generic architecture for on-chip packet-switched interconnections design, automation, and test in europe. pp. 250- 256 ,(2000) , 10.1145/343647.343776
Igor Loi, Federico Angiolini, Luca Benini, Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow Nano-Net '07 Proceedings of the 2nd international conference on Nano-Networks. pp. 15- ,(2007) , 10.4108/ICST.NANONET2007.2033
Abbas Sheibanyrad, Alain Greiner, Ivan Miro-Panades, Multisynchronous and Fully Asynchronous NoCs for GALS Architectures IEEE Design & Test of Computers. ,vol. 25, pp. 572- 580 ,(2008) , 10.1109/MDT.2008.167
Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, N. Vijaykrishnan, Chita R. Das, MIRA ACM SIGARCH Computer Architecture News. ,vol. 36, pp. 251- 261 ,(2008) , 10.1145/1394608.1382143
E. Beigne, F. Clermidy, P. Vivet, A. Clouard, M. Renaudin, An asynchronous NOC architecture providing low latency service and its multi-level design framework ieee international symposium on asynchronous circuits and systems. pp. 54- 63 ,(2005) , 10.1109/ASYNC.2005.10
S. Ogg, E. Valli, B. Al-Hashimi, A. Yakovlev, C. D'Alessandro, L. Benini, Serialized asynchronous links for NoC design, automation, and test in europe. pp. 1003- 1008 ,(2008) , 10.1145/1403375.1403617
Chih-Mou Tseng, Ang-Chih Hsieh, Hung-Chun Li, TingTing Hwang, Min-Hsiu Tsai, Ming-Tung Chang, TSV redundancy: architecture and design issues in 3D IC design, automation, and test in europe. pp. 166- 171 ,(2010) , 10.5555/1870926.1870967
R. Ginosar, Fourteen ways to fool your synchronizer symposium on asynchronous circuits and systems. pp. 89- 96 ,(2003) , 10.1109/ASYNC.2003.1199169