Analysis and Modeling of Clock-Jitter Effects in Delta-Sigma Modulators

摘要: The quest for higher data rates in state-of-the-art wireless standards and services calls wideband high-resolution data-converters transceivers. While modern integrated circuits (IC) technologies provide high cut-off frequencies ( ) transistors hence allow the operation at speeds, main limitation against increasing speed of is problem clock-jitter. Clock-jitter a common associated with clock generators due to uncertainty timing edges caused by finite phase-noise (PN) generated waveform. Particularly, noise components induced several sources system providing (e.g. phaselocked loop, PLL) add waveform cause zero-crossing instants from cycle cycle. Figure 1 shows survey chart analog-todigital converter (ADC) implementations reported IEEE International solid-state conference (ISSCC) VLSI Symposium since 1997 [1]. straight lines show on achievable signal-to-noise ratio (SNR) clock-jitter jitter root-mean square (rms) values 1ps 0.1ps. As can be seen chart, performance most ADCs falls below line corresponding rms jitter, few reside range between 0.1ps, almost all ADC so far are beyond 0.1ps line. This means that terms SNR specification