A continuous-time /spl Sigma//spl Delta/ Modulator with reduced sensitivity to clock jitter through SCR feedback
作者： M. Ortmanns , F. Gerfers , Y. Manoli
关键词: Delta-sigma modulation 、 Delta modulator 、 Resistor 、 Thyristor 、 Jitter 、 Electronic engineering 、 Control theory 、 Sensitivity (control systems) 、 Pulse-width modulation 、 Physics 、 Sigma
摘要: This paper presents a means to overcome the high sensitivity of continuous-time sigma-delta (/spl Sigma//spl Delta/) modulators clock jitter by using modified switched-capacitor structure with resistive element in feedback digital-analog converter (DAC). The reduced is both simulated and proven measured results from two implemented third-order modulators. Additionally, nonideal behavior analyzed analytically simulations.
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