Method of and apparatus for store-in second level cache flush

作者: Donald C. Englin , Donald W. Mackenthun , Mitchell A. Bauman

DOI:

关键词: Page cacheComputer hardwareCache coloringCache pollutionComputer scienceCache invalidationMESI protocolSmart CacheCacheCache algorithms

摘要: Flush apparatus for a dual multi-processing system. Each system has number of processors, with each processor having store in first-level write through cache to second-level cache. A third-level memory is shared by the and caches being globally addressable all memory. Processors can local have access remote via storage controller. coherency scheme provides indicators line showing which ones are valid been modified or different than what reflected corresponding third level The flush uses these two transfer lines that within address range modified, back prior dynamically removing resources due either maintenance dynamic partitioning. prevents loss data during such process inherent nature second

参考文章(21)
Russ W. Herrell, Thomas P. Morrissey, User scheduled direct memory access using virtual addresses ,(1991)
Zahir Ebrahim, Satyanarayana Nishtala, William C. Van Loo, Kevin Normoyle, A fast, dual ported cache controller for data processors in a packet switched cache coherent multiprocessor system ,(1996)