Synchronous type semiconductor memory
作者： Atsushi Takasugi
DOI:
关键词: Synchronous circuit 、 Dram 、 Semiconductor memory 、 Computer hardware 、 Signal 、 Computer science
摘要: A DRAM is capable of regulating an output timing a read data. The the data can be regulated by which has circuit (127) for counting number clock pulses until transferred to latch (121) and (129) outputting counted number. (125) regulate in response external input signal.
google.co.uk参考文章(7)
Yukihiro Nishiguchi, Memory arrangement with means for interfacing a central processing unit ,(1981)
Hidenori Nomura, Tomio Nakano, Dynamic random access memory having improved refresh timing ,(1989)
Yoshihiro Takemae, Tsuyoshi Ohira, Tomio Nakano, Shigeki Nozaki, Masaru Satoh, Semiconductor memory device with internal control signal based upon output timing ,(1990)
Okada Masaya, DYNAMIC MEMORY DEVICE ,(1990)
Takagi Haruo, MEASUREMENT SYSTEM FOR MEMORY ACCESS TIME ,(1978)
Saito Takashi, SETTING SYSTEM FOR MEMORY ACCESS TIMING ,(1988)