Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order

摘要: A controller for a synchronous DRAM is provided maximizing throughput of memory requests to the DRAM. The maintains spacing between commands conform with specifications DRAMs while preventing gaps from occurring in data slots Furthermore, allows and be issued out order so that may maximized by overlapping required operations which do not specifically involve transfer. To achieve this throughput, are tagged indicating sending order. Thereafter, arbitrated when conflicting queued arbitration process then decoded simultaneously updating scheduling constraints. further qualified based on constraints command stack request developed modifying update queues. also functions receiving clock signal generating an SDRAM dividing signal.