Multiprocessor system having controller for controlling the number of processors for which cache coherency must be guaranteed

摘要: To provide a large scale multiprocessor system capable of executing an area limited cache coherency control implementing high speed operation while substantially reducing the amount processor-to-processor communications there is provided translation lookaside buffer which retains attribute information defining limitable coherent to maintain data consistency among caches, and processor memory interface unit includes identifies whether required only within particular cluster processors or for every one memories in clusters throughout system, on basis contents information. Further, another version each may be with export directory registers identifier whose copy cached other clusters. Thereby, latency procedures can reduced greatly, since dependence various characteristics data. it also possible greatly reduce inter-cluster communication quantities, no longer necessary broadcast all upon occasion read/write.