Memory clock slowdown
作者： Sean Jeffrey Treichler , Adam E. Levinthal , Jonah M. Alben
DOI:
关键词: Clock signal 、 Computer hardware 、 CPU multiplier 、 Synchronous circuit 、 Clock gating 、 Interleaved memory 、 Clock domain crossing 、 Clock skew 、 Digital clock manager 、 Computer science
摘要: Circuits, methods, and apparatus for slowing clock circuits on a graphics processor integrated circuit in order to reduce power dissipation. An exemplary embodiment of the present invention provides having two memory clocks, specifically, switched an unswitched clock. The frequency is reduced under specific conditions, while remains fixed. In embodiment, when related graphics, display, scaler, frame buffer are not requesting data, or such data requests can be delayed. Further refinements provide circuits, ensuring that signals remain in-phase aligned with each other.
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