Network-on-Multi-Chip (NoMC) with Monitoring and Debugging Support

摘要: This paper summarizes recent research on network-on-multi-chip (NoMC) at Poznan University of Technology. The proposed network architecture supports hierarchical addressing and multicast transition mode. Such an approach provides new debugging functionality hardly attainable in classical hardware testing methodology. A transmission also enables real-time packet monitoring. introduced features NoC allow to elaborate a model video codec that utilizes distributed processing many FPGAs. Final performance the designed was assessed using AVC coder multi-FPGA platforms. In such system, mode yields overall gain bandwidth up 30%. Moreover, synthesis results show basic components Verilog language are suitable easily synthesizable for FPGA devices. Keywords—debugging, FPGA, multi-chip, NoC, coding.