On-chip networks: a scalable, communication-centric embedded system design paradigm

摘要: As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks previous designs with the effort largely invested into new parts. More more processor cores large, reusable components are being integrated on a single silicon die but communication infrastructure has been difficult. Buses point to connections, that have main means connect today, will not result in scalable platform architecture for billion transistor era. can cost efficiently few tens components. Point connections between partners practical even fewer die, performance bottlenecks long, global wires preclude buses. Therefore, on-chip playing an increasingly dominant role system-on-chip designs. With super-abundance cheap, function-specific IP cores, focus weakest link: efficient communication. Future overcome limits bus-based systems by providing higher bandwidth, flexibility solving clock skew problem chips. It may, however, present problems: power consumption harder-to-predict patterns. Solutions these problems may complete overhaul SOC methodologies communication-centric style. The envisioning upcoming possible benefits led intensified research field what called NoCs: Networks Chips. term NoCs used broad meaning, encompassing hardware infrastructure, middleware operating system services, methodology tools map applications onto network chip. This paper discusses trends designs, critiques opportunities NoC paradigm, summarizes activities, outlines several directions future research.