System and method for controlling power states of a memory device via detection of a chip select signal

作者: Michael W. Williams , James M. Dodd

DOI:

关键词: Chip selectMemory controllerComputer scienceSense amplifierMemory bankMemory rankSemiconductor memoryMemory refreshRegistered memoryComputer hardware

摘要: A memory system and a method for controlling power states of device, or portion thereof, are provided. The includes devices, such as DRAMs, controller, chip select lines, logic detecting signals from the lines. Each therein, is connected to controller by line. line allows transmission signal corresponding receive commands. Logic provided detect signal. When detects that in state lower than its idle state, automatically moved higher state.

参考文章(4)
Todd W. Bystrom, Craig E. Hampel, Richard M. Barth, Bradley A. May, Paul G. Davis, Ely K. Tsern, Frederick A. Ware, Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain ,(1998)
Frederick A. Ware, Matthew M. Griffin, Mark A. Horowitz, Richard M. Barth, James A. Gasbarro, John B. Dillon, Method and apparatus for power control in devices ,(1993)
Frederick A. Ware, Abhijit M. Abhyankar, David Nguyen, Andrew V. Anderson, Craig E. Hampel, Richard M. Barth, Peter D. MacWilliams, Paul G. Davis, James A. Gasbarro, Donald C. Stark, Thomas J. Holman, High performance cost optimized memory with delayed memory writes ,(1998)
Michael R. Hereth, Patricia A. Martin, Pseudo-static memory subsystem. ,(1987)