Error correction circuit
作者： O Patent Div. Toshiba Corp. Nagumo , Tadashi C , O Patent Div. Toshiba Corp. Kojima , O Patent Div. Toshiba Corp. Inagawa , Jun C
DOI:
关键词: Code (cryptography) 、 Galois theory 、 Algorithm 、 Binary number 、 Error location 、 Error detection and correction 、 Field (mathematics) 、 Mathematics 、 Basis (linear algebra)
摘要: An error correction circuit for detecting and correcting a plurality of errors in codewords made up k data n - inspection symbols In the playback from recorded medium each symbol m binary bits information using Reed-Solomon code detection so that location polynominal a(x) = x8 + σ1xe-1 ... σe where e is number coefficients σ1 to are related syndromes Si generated by equation Si+e field elements α' Galois GF(2m). The includes: (a) means (12) generating S0, S,, S2 S3 codewords; (b) (17) effecting following three calculations on basis S1, syndrome r3, r2 r, represent values respective calculations; (c) (23) judging whether condition r3 ≠ 0 or 0; (d) first processing (17, 25 32) finding locations determining roots as polynominal, when conditions confirmed x represents locations; (e) second 25-32) root under
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