Error correction code pipeline for interleaved memory system
作者： Michael L. Longwell , Keith D. Matteson
DOI:
关键词: CPU cache 、 Error detection and correction 、 Pipeline (computing) 、 Computer science 、 Process (computing) 、 Computer hardware 、 Data stream 、 Central processing unit 、 Multiplexing 、 Interleaved memory
摘要: A data stream process pipeline and method of transferring from a storage device to central processor unit (CPU) or cache memory includes an input latch arrangement, error correcting circuitry, output arrangement. In embodiments the present invention arrangements include two latches means for multiplexing outputs latches.
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