作者: Yahya Jan , Lech Jozwiak
DOI: 10.1007/978-3-642-00641-8_39
关键词: Hardware acceleration 、 Computer science 、 Electronic design automation 、 Architecture 、 Multimedia 、 Coding (social sciences) 、 Embedded system 、 Context-adaptive binary arithmetic coding 、 Binary number 、 Data compression 、 Display resolution
摘要: The future high quality multimedia systems require efficient video coding algorithms and corresponding adaptive high-performance computational platforms. In this paper, we survey the hardware accelerator architectures for Context-based Adaptive Binary Arithmetic Coding (CABAC) of H.264/AVC. purpose is to deliver a critical insight in proposed solutions, way facilitate further research on architectures, architecture development methods supporting EDA tools. are analyzed, classified compared based core acceleration concepts, algorithmic characteristics, resolution support performance parameters, some promising design directions discussed.