Vertical gate NAND memory devices

作者: Bruce Lynn Bateman

DOI:

关键词: Bubble memoryStack (abstract data type)Sense amplifierOptoelectronicsLine (electrical engineering)NAND gateElectronic engineeringMemory cellPhysics

摘要: In an example, a device comprises vertical stack of memory cells. Each cell the may include more than one element. A first gate line be coupled to elements in each cell, and second cell. The electrically isolated from line.

参考文章(13)
Sung-Min Hwang, Han-soo Kim, Vertical Structure Non-Volatile Memory Device ,(2011)
Nima Mokhlesi, Roy Scheuerlein, Method of making three dimensional NAND memory ,(2007)
Yoon Kim, Jang-Gn Yun, Se Hwan Park, Wandong Kim, Joo Yun Seo, Myounggon Kang, Kyung-Chang Ryoo, Jeong-Hoon Oh, Jong-Ho Lee, Hyungcheol Shin, Byung-Gook Park, Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray IEEE Transactions on Electron Devices. ,vol. 59, pp. 35- 45 ,(2012) , 10.1109/TED.2011.2170841
Hang-Ting Lue, Tzu-Hsuan Hsu, Yi-Hsuan Hsiao, S. P. Hong, M. T. Wu, F. H. Hsu, N. Z. Lien, Szu-Yu Wang, Jung-Yu Hsieh, Ling-Wu Yang, Tahone Yang, Kuang-Chao Chen, Kuang-Yeu Hsieh, Chih-Yuan Lu, A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device symposium on vlsi technology. pp. 131- 132 ,(2010) , 10.1109/VLSIT.2010.5556199
Chulmin Park, Wonjoo Kim, Juhwan Jung, Yoondong Park, Taehee Lee, Inkyong Yoo, Hyoungsoo Ko, Junghun Sung, Sangmoo Choi, Multi-layered Vertical Gate NAND Flash overcoming stacking limit for terabit density storage symposium on vlsi technology. pp. 188- 189 ,(2006)
Moon-Sik Seo, Bong-Hoon Lee, Sung-kye Park, Tetsuo Endoh, A Novel 3-D Vertical FG NAND Flash Memory Cell Arrays Using the Separated Sidewall Control Gate (S-SCG) for Highly Reliable MLC Operation international memory workshop. pp. 1- 4 ,(2011) , 10.1109/IMW.2011.5873208