Pipelined multiple issue packet switch

摘要: A pipelined multiple issue architecture for a link layer or protocol packet switch, which processes packets independently and asynchronously, but reorders them into their original order, thus preserving the incoming order. Each stage of pipeline waits immediately previous to complete, causing switch be self-throttling allowing differing protocols features use same architecture, even if possibly requiring processing times. The is scaleable greater parallel packets, tunable engine architectures, interface speeds widths, clock rates buffer sizes. comprises fetch stage, fetches header one plurality caches, switching comprising engines, each asychronously reads from corresponding makes decisions, write reorder memory, memory in packets' post-processing post-process queue engine, performs protocol-specific on packets.