Mitigating Limited PCM Write Bandwidth and Endurance in Hybrid Memory Systems

摘要: With the rise of big data and cloud computing, there is increasing demand on memory capacity to solve problems large sizes consolidate computation tasks. For systems, DRAM a significant source energy consumption. Non-volatile memory, such as Phase-Change Memory (PCM), promising technology for constructing energy-efficient memory. Unlike DRAM, PCM has negligible background (static) power allows high density packaging. But also limited write bandwidth endurance. Hybrid systems have been proposed combine high-density low standby with good performance DRAM. This thesis addresses two challenges which are unique hybrid systems. The first challenge bandwidth, can become bottleneck. second non-contiguous physical due retired pages. Since cells endurance, it inevitable gradually increased number uncorrectable errors during lifetime. pages that detected normally by OS, create unusable “holes” in These holes make difficult construct traditional superpages, incur overhead. In this thesis, I propose three solutions address these challenges. First, observed an unbalanced distribution modified bits among chips significantly increases time hurts effective bandwidth. new XOR-based mapping schemes between program improve throughput spreading evenly chips. Second, compressed cache scheme reduce traffic PCM. A adaptive delta-compression technique used achieve compression ratio. Third, Gap-tolerant Sequential Mapping, page scheme, superpages from simple practical designs, be easily adopted future