Adaptive Cache Compression for High-Performance Processors

摘要: Modern processors use two or more levels ofcache memories to bridge the rising disparity betweenprocessor and memory speeds. Compression canimprove cache performance by increasing effectivecache capacity eliminating misses. However,decompressing lines also increases accesslatency, potentially degrading performance.In this paper, we develop an adaptive policy thatdynamically adapts costs benefits of cachecompression. We propose a two-level hierarchywhere L1 holds uncompressed data L2cache dynamically selects between compressed anduncompressed storage. The L2 is 8-way set-associativewith LRU replacement, where each set can storeup eight but has space for only fouruncompressed lines. On reference, LRUstack depth size determine whethercompression (could have) eliminated miss incurs anunnecessary decompression overhead. Based on thisoutcome, updates single globalsaturating counter, which predicts whether allocatelines in form.We evaluate compression usingfull-system simulation range benchmarks. Weshow that improve formemory-intensive commercial workloads up 17%.However, always using hurts performancefor low-miss-rate benchmarks-due unnecessarydecompression overhead-degrading byup 18%. By monitoring workload behavior,the achieves comparable benefitsfrom compression, while never performanceby than 0.4%.