Clock apparatus and data processing system
作者： G Grant
DOI:
关键词: Clock rate 、 Computer science 、 Digital clock manager 、 Computer hardware 、 CPU multiplier 、 Clock signal 、 Clock gating 、 Clock angle problem 、 Clock skew 、 Clock domain crossing
摘要: Disclosed is a clock apparatus for use in data processing system. The pulse width made substantially equal to the maximum latch delay (MLD) plus skew (CS) obtaining minimum number of circuits relative frequency.
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