作者: S. Dhong , R. Jewett , T. Van Duzer
DOI: 10.1109/TMAG.1983.1062400
关键词: Signal edge 、 Analog-to-digital converter 、 Successive approximation ADC 、 Josephson effect 、 Physics 、 Comparator 、 Electrical engineering 、 SQUID 、 Voltage divider 、 Flash ADC
摘要: This paper describes the comparator stage of a Josephson junction 4-bit A/D converter. It utilizes periodic nature SQUID's to make A/DC with only four comparators for parallel conversion. A new design symmetrical three-junction SQUID provides identical lobes beyond required. The necessary short aperture time is obtained by imbedding in self-gating-AND circuits that detect input signal during rising edge clock. binary resistor divider correct proportions comparators. Both computer simulation results and low-frequency test are presented.